1. Field of the Invention
The present invention relates to integrated circuit design, and, more particularly, to the automated design of radio frequency and high speed analog integrated circuits.
2. Description of Related Art
The electrical design and physical implementation of integrated circuits, especially radio frequency and high speed analog circuits, are tightly coupled. To this end, parasitic electrical effects resulting from the routing of conductors to interconnect circuit devices must be taken into consideration during front-end electrical synthesis. On the other hand, the back-end layout of circuit devices must be carried out in such a way that target performance specifications are guaranteed to be met. In practice, several iterations between circuit design and layout are typically required to achieve final design closure. This process is time consuming and is usually guided only by a designer's experience and expert knowledge about the circuit and layout. Although separate analog layout tools and circuit synthesis tools are available, heretofore no tool has been available to automate the overall process.
A drawback of existing layout approaches is that they all assume the circuit schematic is fixed when laying out the circuit devices. Consequently, the device parameters for the circuit devices utilized to implement the circuit are translated into hard constraints for layout. So, if one intermediate placement of a circuit device or the routing of an interconnecting conductor violates one performance specification, the entire design is marked as costly or infeasible. In this way, the layout of circuit devices and the routing of interconnecting conductors is over restricted.
Therefore what is needed is a method and apparatus for automatically generating and revising a layout of circuit devices and the routing of the interconnecting conductors of a circuit whereupon the circuit meets or is within predetermined tolerances of target performance specifications for the circuit.